Plasma Technology  


SEM image of a cross section of a 50nm
ICP-PECVD SiN RT deposited on
200nm metal with good step coverage


High quality SiN films deposited
on Si and GaAs substrates

Temperature ~ 20ºC

Pressures < 10mT

Refractive Index 1.8 2.5 @ 632.8nm

Deposition Rate 12-17 nm/min

Si/N Ratio 0.7 - 0.8

H atm % < 3 %

Uniformity ~ ±5 % across a 4 wafer

Stress -27 - + 25 MPa

Low Temperature SiN ICP - PECVD

Plasmalab System 100
with ICP180

with kind permission
H Zhou, K Elgaid, C Wilkinson, I Thayne
Nanoelectronics Research Centre
Glasgow University

Low temperature ICP-CVD SiN for
MIM Capacitor technology

Leak current of a (10x20) µm MIM capacitor with 120 nm SiN
deposited at 20°C and compared with that of 170nm SiN
deposited at 300°C using the standard PECVD

Electrical properties of ICP-CVD SiN deposited @ 20ºC
 comparable with PECVD SiN deposited @ 300ºC
5nm thin film with excellent coverage and no shorting
 over a metal step of 150nm
Capacitance increased 13 fold as the SiN film thickness
 reduced from 120nm to 5nm
Capacitors and other passive require SiN can be done
 at later stage after gates level
Lift-off capability to avoid dry etch step and reduce
 MMIC fab cycle time

SiGe active device technology using
low temperature ICP-CVD SiN

70nm Si/SiGe n-MIS Gate devices have been realised
by using SiN deposited at 20 ºC

Low thermal budget

Robust and high yield process, > 95% yield

SiN deposited prior to gate metal

Lift-off process without dry etch SiN

EOT ~ 2.5 nm for 5nm SiN

IR absorption spectra

ICP-CVD SiN no N-H bonds
deposited @ 20ºC & 300ºC

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