Plasma Technology  

Tri-layer resist scheme for nano-silicon etching

Aiming at sub-20nm half-pitch
with the mixed Si ICP process:

The high resolution top resist pattern is
transferred into the thicker spin-on-carbon
(SoC) by the tri-level technique.
The SoC mask is then used to etch deep
into the Si.

with kind permission
A. Frommhold and A.P.G. Robinson,
University of Birmingham

ICP etching of the thin top Si

ICP etching of the middle C film

bottom Si etching with 20 nm resolution

bottom Si etching with 40 nm resolution



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